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DDR5 and LPDDR5 Protocol Debug and Validation Solutions

Keysight U4164A05 June 2018 - Keysight Technologies announced the first DDR51 and LPDDR52 Protocol Debug and Validation solutions. These solutions, when used in conjunction with Keysight's U4164A logic analyzer, enable designers of enterprise servers, mobile devices, and wireless equipment to debug and test DDR5 and LPDDR5 systems as well as validate protocol compliance.

Industry adoption of the 5G New Radio (NR) standard requires data servers and mobile devices to offer higher data rates and performance, as well as support lower power consumption. DDR5 Memory delivers higher bandwidth and performance improvements that the next generation of cloud servers need to support 5G use cases. LPDDR5 enables mobile devices to support increased bandwidth, improved performance, and lower power consumption.

New solutions from Keysight provide engineers with critical insight into the behavior of the DDR5 or LPDDR5 bus traffic by capturing and analyzing live traffic. This is achieved by tracing signals in the memory bus between the processor and memory devices.

 Keysight provides comprehensive design test solutions for next generation cloud servers by combining its DDR5 Analysis and Compliance Validation software and U4164A logic analyzers with DDR5 interposers3.

"Critical cloud and device applications require reliable and high performing DDR5 memory technology. Keysight's DDR5 and LPDDR5 Memory Protocol Debug and Validation solutions enable device designers to accelerate high-speed digital interface innovations in support of next generation devices and future 5G use cases," said Kailash Narayanan, vice president and general manager for Wireless Device and Operators at Keysight.

Keysight offers a comprehensive portfolio of solutions to address the entire DDR5 technology lifecycle from design to debug, compliance validation, and manufacturing testing of mature products. Common user interfaces, combined with extensive test coverage across the workflow creates a cost-efficient test environment that offers the superior correlation of measurements necessary to resolve issues related to memory traffic, signal integrity and power integrity.

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