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Test Vector Interface for IEEE1450 (STIL)

09 July 2010 - GOEPEL electronic introduces a new test vector interface as a new extension of its software platform SYSTEM CASCON. The newly developed vector link is based on IEEE1450 – Standard Test Interface Language (STIL) – and enables the seamless coupling during test pattern export, in particular to chip testers.

“A whole series of chip manufactures already use our system to validate prototypes on board level. The universal STIL interface provides them a solution for seamless migration of complete test pattern to existing production testers”, announces Bettina Richter, Corporate Marketing Manager with GOEPEL electronic. “At the same time, this system extension enables a yet better compatibility and networking ability of our tools to available EDA and CAT environments on chip and at board level.”

The IEEE1450 interface’s central element is an export post processor that transfers existing test pattern to a respective STIL format. In addition to serial scan data, also parallel vectors including, expect and mask values as well as the necessary timing information are exported.

Beyond Std. IEEE1149.1 tests, the export post processor supports the transfer of IEEE1149.6 operations for the test of Advanced Digital Networks.

On this basis, test pattern generated and verified in SYSTEM CASCON™ can seamlessly be migrated to a production tester. It does not matter whether test pattern have been generated automatically with ATPG or manually scripted. An import of IEEE1445 (DTIF) simulation data into the system environment with subsequent validation and later export as IEEE1450 is also possible. Additionally, identical cross transfers are supported for JESD71 (STAPL), SVF (Serial Vector Format), TDS (TSSI) and further formats.

The new vector link for IEEE1450 is integrated as standard in the platform license from SYSTEM CASCON™ version 4.5.3 and is activated by the licence manager.

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