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Advantest enhances the T2000 SOC Test Platform

02 December 2010 – Advantest Corporation announced three new modules and an infrastructure enhancement, named Enhanced Performance (EP) Package, for the T2000 SOC test platform. The EP Package and the new module designs support Functional Test Abstraction (FTA), enabling test engineers to execute system level IC design verification programs on ATE, substantially reducing the lead time from design to functional testing of complex SOCs at the protocol level.

In addition, the new 1GDM module, DPS90A module, and GPWGD module offer twice the parallel test capability of previously available modules by featuring 2x greater resources per module, and allowing a maximum of 8192 pins to be installed in the test head. The new EP Package will enable multi-site CPU configurations with near zero compute overhead for the same cost as the previously available single-site CPU configurations, improving throughput, reducing test costs, and time-to-market (TTM), while facilitating easy test program development, simulation, and debugging. Customers are invited to preview these new technologies at SEMICON Japan 2010, December 1-3, at Chiba's Makuhari Messe.

The increasing integration of multi-functional ICs for mobile devices, combined with the accelerating trend for chip-makers to enhance competitiveness by adding functionality, is driving the need for test solutions which can lower test costs and help shorten TTM. Advantest’s new modules and EP Package respond to these needs by further enhancing the performance of the T2000, Advantest’s flagship SoC test platform. By installing the three new modules, users can reduce the number of instruments used, while doubling the parallelism of previous solutions. The new EP Package helps to reduce test costs and time-to-yield with expanded functionality that enables existing T2000 users to implement true concurrent test, reduced compute overhead and increase system utilization for test debug and production test.

www.advantest.com


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