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PCI Express Protocol Exerciser for L1 Substate Validation

Keysight U4305B01 July 2015 – Keysight Technologies introduced the U4305B PCI Express protocol exerciser for engineers developing PCIe Gen3 systems. The U4305B exerciser offers a broad range of PCIe test tools for validating Gen1, Gen2 and Gen3 operation for all lane widths up to x16. The tools address PCIe developers’ needs, including providing ways to test new technologies like NVMe (Non-Volatile Memory Express) and L1 substate operation.

Starting with the early PCIe implementations, low power states have always been important to developers. Now, PCIe has new standards for extremely low power called L1 substate. Using a sideband signal, CLKREQ#, to allow devices to shut down the clock and even remove keeper voltages, new PCIe devices are more power efficient than ever. The U4305B exerciser is designed to verify these low-power implementations. A built-in test bench allows users to generate automated tests of PCIe or NVMe operations. The test bench comes with scripts that validate the operation from ASPM or PCI-PM L1 substates. These prewritten tests exercise each state to provide pass/fail results that report on control register operation as well as operation of each L1 substate entry/recovery.

An LTSSM test package is available for the U4305B. The package allows engineers to perform link negotiation testing that can thoroughly test a DUT’s LTSSM functions. It also can verify PCIe state transitions and validate state timeouts. More than 50 predefined LTSSM tests assess the DUT’s operation.

“The U4305B exerciser offers a new level of test capabilities for PCIe developers,” said Dave Cipriani, vice president and general manager of Keysight’s Oscilloscope and Protocol Division. “Implementation of PCIe devices requires deep insight, and our customers need tools that enable them to develop the best products.”

For testing NVMe, the U4305B exerciser can emulate either the host or device to submit and execute NVMe commands or create error test sequences. Standardized NVMe testing not only improves adherence to the specification and increases device interoperability, but also decreases test time by providing tests that give developers insight into device operation. Keysight’s implementation uses the NVMe conformance tests as defined by the University of New Hampshire (UNH) Interoperability Lab (IOL). These tests provide pass/fail/warning results with detailed diagnostic information to improve NVMe validation.

The PCI SIG-defined protocol test card is also available for a complete set of pass/fail test results to validate PCIe operation. The PTC test package is the same one used at PCI-SIG workshops.

Engineers can configure the Keysight U4305B exerciser to provide subprotocol layer test and debug for legacy and next-generation PCIe devices. The U4305B exerciser for PCIe is an advanced traffic generator that developers can use to send and respond to TLP, DLLP and physical-layer packets to stimulate PCIe devices and systems.

The U4305B is part of a complete test system from Keysight Technologies that includes the U4301B PCIe protocol analyzer. Engineers can synchronize the test operation of the analyzer and exerciser or even use data captured by the U4301B analyzer to replay on the U4305B exerciser.

Keysight’s enhancements to the PCIe analyzer and exerciser help to make sure engineers have a complete set of tools. For example, the L1 substate testing, data replay and test synchronization all are implemented to enable complete test and verification of PCIe devices.

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