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Integrated Fader for LTE-Advanced 4x4 MIMO and 8x2 MIMO Tests
26 August 2015 – Anritsu has integrated channel fading simulation into its 4G LTE-Advanced Signalling Tester, the MD8430A. The new digital baseband fading options convert the MD8430A into a full-featured fading simulator supporting industry standard 3GPP-defined fading profiles. The MD8430A fading options can be combined with the MD8430A, cutting the need for investment in additional hardware to perform signalling tests under realistic radio frequency (RF) conditions.
This is the first LTE-Advanced signalling solution with built-in fading supporting the 4x4 MIMO downlink configuration.
The MD8430A is trusted by LTE and LTE-Advanced development engineers as the leading signalling tester for simulating LTE networks in the lab. With this release, the versatile MD8430A hardware platform continues to evolve, delivering Anritsu customers exceptional return on investment.
Tall structures, such as buildings and trees, reflect and scatter transmitted radio waves, meaning the receiver actually receives multiple original signals arriving from ‘multipaths’ with different strengths, times, and directions. A key feature of LTE-Advanced is the Multiple Input Multiple Output (MIMO) antenna system that improves device performance by exploiting multipaths. To test such MIMO devices thoroughly, multipath fading effects must be applied accurately to every antenna in a reproducible manner.
Using internal digital baseband processing, the MD8430A applies multipath effects during test execution, and the Rapid Test Designer (RTD) software provides testers with an integrated environment for creating and running fading simulation tests. Support for LTE-Advanced features, such as Carrier Aggregation and MIMO, make the MD8430A the ideal solution in helping leading chipset designers build the next generation of high-performance mobile devices. In addition to testing devices over an RF connection, the MD8430A with fading option also supports a slow-clock digital interface to verify designs in a simulation environment before starting expensive ASIC production.
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