News - Board and System Test

In-System Emulation Technology with total Versatility

01 December 2010 - GOEPEL electronic announces the development of special extended features within the frame of the innovative emulation technology VarioTAP. These three core components extend the so called VarioTAP processor models by new interfaces for the flexible development and execution of completely customised real time and at-speed tests.

“We view the processor emulation test not as an alternative but a perfect addition to Boundary Scan, because it provides very high functional test coverage. That’s why we focused on the strategy to combine both procedures on one platform from the very beginning“, says Thomas Wenzel, Managing Director of GOEPEL electronic’s JTAG Boundary Scan Division. “The new VarioTAP features represent another milestone towards raising the workflow onto the same level as Boundary Scan in terms of openness and flexibility. The synergy between both methodologies even increases."

VarioTAP is a streaming technology for TAP signals (Test Access Ports) and is based on respective processor model libraries. These so called VarioTAP models are structured as intelligent IP and support a fast Flash programming as well as bus emulation tests (BET) and system emulation tests (SET). The three new interfaces now provide the opportunity to execute user-specified verification, test and diagnostic routines.

From now on, VarioTAP- models contain a complete software framework for bus and system emulation, which enables the inclusion and communication of user-defined procedures. Such routines are able to execute complex real time tests incl. DMA and interrupt handlers without considering the processor initialisation. Examples for practical implementation of performance tests of RAM, stress tests of special on-board components to detect thermal or EMV problems, stability tests for interfaces and much more.

Furthermore all VarioTAP models for bus and system emulation feature a standard FMC interface. This enables the execution of Functional Micro Code (FMC), a processor-independent, test-oriented Meta language. Applying it users can write and execute algorithmic test models incl. diagnosis without utilising the respective processor’s native tool chain. Due to their independence such scripts are completely portable and administrated in the library just like Boundary Scan device and cluster tests.

The system integrated FMC method basically simplifies the generation and utilisation of emulation tests, making them more effective.

The third interface enables the development of completely customer-specific VarioTAP models, in which users can define and control all IP functions, procedure names and access sequences to the lower levels via a Hardware Abstraction Layer (HAL). With the available Model Development Kit (MDK) users and third parties can independently develop and control application-specific VarioTAP models.

The use of VarioTAP does not require expert background knowledge, additional development tools or processor-specific pods, which makes the handling easy and uncomplicated. Because no Flash image is required all awkward programming procedures and lengthy boot operations are omitted, which ensures a high work efficiency and throughput in production.

The new VarioTAP features are supported as standard starting from SYSTEM CASCON version 4.5.3 and are activated by the licence manager like the system software. SYSTEM CASCON is a professional JTAG/Boundary Scan development environment developed by GOEPEL electronic with currently more than 40 completely integrated ISP, test and debug tools. Regarding the hardware, VarioTAP is completely supported by the controllers of the SCANBOOSTER family, as well as by the hardware platform SCANFLEX.

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