Ultra-fast Programming of FPGA Boot Flash

11 April 2012 - GOEPEL electronic announced the development of an additional ChipVORX model library series for accelerated in-system programming (ISP) of FPGA Boot Flash components. The ChipVORX models developed in cooperation with the Tallinn/Estland based Company Testonica are structured modularly as intelligent IP. They enable the ultra-fast parallel programming of every kind of FPGA Boot Flash components at full workflow automation.

“Modern system developments are increasingly based on the utilisation of powerful FPGA platforms and require for efficient solutions in in-system programming of the necessary Boot Flash in particular in the production process. Our new ChipVORX models continue to achive these demands”, says Thomas Wenzel, GOEPEL electronic’s managing director of the Boundary Scan Division. “The combination of highest performance, automation and synthesis freedom enables users to implement highly efficient programming strategies. At the same time, ChipVORX becomes the most flexible technology in controlling FPGA embedded instruments by far.”

Due to the complete integration of the ChipVORX IP the recognition of the structural connections between Flash target and FPGA is done as automatically as the succeeding script file generation. The programming is based on a standardised IEEE1149.1 TAP (Test Access Port) and can be executed on each run time station without further options. Thereby, parallel programming on one board and Gang applications are naturally supported.

Because of the ChipVORX IP’s independence of the target to be programmed the Flash type imposes no restrictions. As the same system libraries as for a “normal” Boundary Scan programming are used, users may update new Flash models by themselves.

In practice, the ChipVORX IPs can achieve dramatic speed improvements compared to standard Boundary Scan programming procedures. For example, a 128 Mbit Flash can be programmed within 48 seconds only be limited by the Flash internal programming speed. Utilising the available 16 fold Gang options for mass production the programming time is reduced to 3 seconds.

At the moment, the ChipVORX models for Flash programming are available for all Altera and Xilinx FPGA families; additional ones are under development.  The usage of the IP does neither require expert background knowledge nor special FPGA tools or programmers. Due to the OEM cooperation with all leading vendors of In-Circuit Testers (ICT), Manufacturing Defect Analysers (MDA), Flying Probe Testers (FPT) and Functionality Testers (FT), the new solution is available for production with immediate effect.

The new ChipVORX IP models are supported as standard starting from SYSTEM CASCON version 4.6.1 and are activated by the licence manager like the system software. SYSTEM CASCON is a professional JTAG/Boundary Scan development environment, developed by GOEPEL electronic with currently 47 completely integrated ISP, test, and debug tools. Regarding the hardware, VarioTAP is completely supported by the controllers of the SCANBOOSTER family, as well as by the hardware platform SCANFLEX.