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Boundary Scan based Programming Tools for Cypress PSoC3 Devices

10 August 2012 - In close cooperation with Cypress, GOEPEL electronic has developed a dedicated VarioTAP model library for the PSoC3 programmable System on Chip series. VarioTAP is an universal processor centric emulation technology for programming, test and design validation. The solution enables the onboard programming of the PSoC3 devices at system level throughout the entire product life cycle.

The user benefits are significant increases in programming efficiency and savings in additional investments for other test and programming equipment. The libraries, described as VarioTAP models, are structured modularly as intelligent IP, enabling a complete fusion of programming and test via processor debug interfaces and other technologies such as Boundary Scan or Chip embedded Instruments on a single platform.

“We are very excited that our tools have been qualified by Cypress for their powerful PSoC3 devices which now enables the support of many applications and customers in the automotive, industrial, medical and consumer market throughout the entire product life cycle”, says Thomas Wenzel, Managing Director of GOEPEL electronic’s JTAG Boundary Scan Division. “In particular in the manufacturing process users can now rely on our production equipment for single and gang applications which makes programming reliable and efficient”.

“The qualification of GOEPEL electronic’s hardware and software for use with our PSoC 3 devices is an important step in expanding the Cypress third party ecosystem”, said Mark Saunders, PSoC Software - Applications and Marketing Manager. “It will prove a benefit for our customers and their JTAG specific programming and testing applications.”

The Cypress PSoC3 are true programmable System on Chip devices combining high precision analogue units with flexible digital periphery, ultra-low power, embedded processing and PLD based logic. Programming of the embedded Flash and debugging can be executed via the JTAG interface or the SWD interface.

VarioTAP enables the reconfiguration of the integrated processor into a native design embedded test and programming controller via the JTAG Debug port. The IP contains all necessary functions to control the entire execution and for matching the stringent timing requirements. Thus, the use of VarioTAP® does not require expert background knowledge, additional development tools or processor-specific pods, which makes the handling easy and uncomplicated.

The new VarioTAP IP models are supported in the development and execution software CASCON GALAXY starting from version 4.6.0, and are activated by the licence manager in the system software. CASCON GALAXY is a professional JTAG/Boundary Scan development environment, developed by GOEPEL electronic with currently 45 completely integrated ISP, test, and debug tools. The utilisation of the respective VarioTAP models is free of charge for existent customers with valid software maintenance contracts.

In terms of hardware, the Cypress PSoC3 processor models are supported by the Boundary Scan hardware SCANFLEX. SCANFLEX supports all host platforms such as PXI, PXIe, PCI, PCIe, USB, Fast Ethernet etc. Therefore, customers have the choice for many different bus platforms to program your PSoC3 devices.

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