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Tektronix adds PCIe 3.0 Receiver Test Support for BERTScope

28 June 2011 – Tektronix announced the availability of a draft method of implementation (MOI) for PCI Express 3.0 receiver testing using the BERTScope BSA85C. This capability complements previously introduced solutions for verifying transmitter and channel performance of PCIe 3.0 designs using DPO/DSA/MSO70000 series oscilloscopes and Tektronix TLA7SA16 and TLA7SA08 Logic Protocol Analyzer modules, bus support software, and probing solutions.

“The Tektronix BERTScope team has been working closely with PCI-SIG during the development of the standard for Gen3 receiver testing, and we have successfully participated in all the workshops and plug fests to ensure the BERTScope meets the test requirements outlined in the draft CEM specification,” said Roy Siegel, general manager, Oscilloscopes, Tektronix.  “This early work ensures that the BERTScope will fully meet customers’ needs for PCIe 3.0 receiver compliance and margin testing.”

The full set of receiver test challenges are addressed in the MOI including putting devices into loopback, setting and calibrating the required stresses and pre-emphasis, and performing jitter tolerance tests.  Additionally receiver test challenges are heightened due to closed eyes on returning signals from the DUT.  The BERTScope MOI addresses these concerns and offers a number of solutions.

The BERTScope family of products allow design engineers to not only make compliance measurements to fulfill standard test requirements, but also offers a full suite of characterization and debug features to assist with margin testing and provide insight into the failure mode of devices.

The BERTScope is complemented by the DPP125B which adds critical pre-emphasis to the stressed pattern, and the CR125Athat recovers the embedded clock to allow for eye diagram analysis on the resulting signal.

Comprehensive PCIe 3.0 Test Solutions

With the over-sampling performance at 100 GS/s, DPO/DSA/MSO70000 Series oscilloscopes deliver the performance and signal fidelity required to meet PCIe 3.0 test challenges. Option PCE3 for these instruments accelerates the analysis and validation of PCIe designs and provides the flexibility to check devices for precompliance or perform device characterization or debug in a single software package.

Serial Data Link Analysis software enables channel de-convolution, convolution and receiver equalization. DPOJET Jitter and Eye-diagram Analysis software provides jitter, eye-diagram and parametric testing.  And the P7520 TriMode Differential Probe is available for validation and debug of chip-to-chip links, including common mode measurements.

These tools also integrate with the TLA7SA16 and TLA7SA08 Logic Protocol Analyzer modules and the TLA7000 Series Logic Analyzers to provide complete visibility of PCIe 3.0 physical and logical layers. In May 2011, the TLA7SA00 won a Test & Measurement World 2011 Best in Test Award in the Bus Analyzers category.


The PCIe 3.0 receiver testing MOI using the BERTScope is available now.

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